1. Field of the Invention
The invention relates to a method for the production of a DRAM cell configuration.
In DRAM cell configurations, that is to say memory cell configurations with dynamic random access, use is made almost exclusively of so-called single-transistor memory cells. A single-transistor memory cell includes a read-out transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge, which represents a logic value, 0 or 1. That information can be read out through a bit line by driving a readout transistor over a word line.
Since storage density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. Since limits are imposed on the reduction of the structure sizes by a minimum structure size F which can be produced by using the respective technology, that is also associated with an alteration of the single-transistor memory cell. Thus, up until the 1 Mbit generation, both the read-out transistor and the storage capacitor were realized as planar components. Starting with the 4 Mbit memory generation, a further reduction in area had to be effected through the use of a three-dimensional configuration of the read-out transistor and the storage capacitor.
One possibility is to realize the storage capacitor in a trench rather than in a planar manner (see, for example, a paper by K. Yamada et al. entitled xe2x80x9cA Deep Trenched Capacitor Technology for 4 Mbit DRAMsxe2x80x9d, in Proc. Intern. Electronic Devices and Materials IEDM 85, page 702).
Another possibility is to use vertical MOS transistors as described in U.S. Pat. No. 5,376,575, for example. In the production method described therein, each vertical MOS transistor encompasses two opposite sides of a trench along which a bit line runs. Doped regions which act as a drain region of the MOS transistors are provided in the upper area of the sides. The surface of the sides is provided with gate oxide. A gate electrode is provided which covers the opposite surface of the gate oxide. The gate electrode is insulated from an inferior, buried bit line and from a superior storage node, in each case by an insulating layer. Shallow trenches which run transversely to the bit lines and in which word lines running transversely to the bit lines are disposed are provided in the surface of the substrate. The word lines laterally adjoin the gate electrode and are thus connected thereto. The smallest memory cell area that can be achieved using that method is 6 F2.
German Published, Non-Prosecuted Patent Application DE 38 44 120 A1 discloses a DRAM configuration in which trenches are provided in a semiconductor substrate. A drain region is provided at the bottom of the trench. A source region is provided at the surface of the substrate. The side walls of the trench are provided with gate oxide and a gate electrode and act as a channel region. The gate electrodes are embedded in an insulation layer in which a contact hole reaches down to the surface of the drain region located at the bottom of the trench and is provided with an electrode. A capacitor is provided laterally with respect to the trench on the surface of the semiconductor substrate. The lateral configuration of the capacitor and the transistor results in an increased area requirement of the memory cell.
A DRAM cell configuration in which read-out transistors are constructed as vertical transistors is mentioned in a paper by P. Chatterjee et al. in IEDM 86 pages 128-131. A read-out transistor has a first source/drain region which annularly surrounds a gate electrode and is part of a bit line. A second source/drain region of the read-out transistor is produced by outdiffusion of dopant of a storage node which is realized in a depression and is disposed underneath the gate electrode. Word lines, which are in part composed of gate electrodes, run above the bit lines. The read-out transistor encompasses at least sides of the gate electrode which are parallel to the bit lines. The area of a memory cell is 9 F2.
German Patent DE 195 19 160 C1 proposes a DRAM cell configuration which includes one vertical MOS transistor per memory cell. A first source/drain region of the transistor is connected to a storage node of a storage capacitor, a channel region of the transistor is annularly enclosed by a gate electrode, and a second source-drain region of the transistor is connected to a buried bit line. The storage capacitor is either a planar capacitor or a stacked capacitor. The DRAM cell configuration can be produced with a memory cell area of 4 F2.
The area of a memory cell of a DRAM in the 1 Gbit generation is intended to be only about 0.2 xcexcm2. In that case, the storage capacitor must have a capacitance of 20 to 30 fF. Such a capacitance can only be achieved at great expense given a cell area of the kind that is available in the 1 Gbit generation, both in the case of planar capacitors and in the case of stacked capacitors: in the case of planar capacitors, it is necessary to apply a capacitor dielectric made of a material having a particularly high dielectric constant. Since the known ferroelectric and paraelectric materials which are suitable therefor contaminate the apparatuses which are usually used to produce DRAMs, the DRAM to be produced must be placed into an additional second apparatus for the application of the dielectric. In the case of the stacked capacitor, a relatively complicated polysilicon structure is required in order to enlarge the area and thus the capacitance of the storage capacitor, which structure is all the more difficult to produce as the cell area becomes smaller.
It is accordingly an object of the invention to provide a method for the production of a DRAM cell configuration, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type, and in which the DRAM cell configuration has single-transistor memory cells as its memory cells and can be produced with the requisite component density for the 1 Gbit generation.
With the foregoing and other objects in view there is provided, in accordance with the invention, a DRAM cell configuration, comprising a substrate of semiconductor material; memory cells each including a read-out transistor integrated in the substrate as a vertical MOS transistor, and a storage capacitor having a storage node; a bit line and a word line; the vertical MOS transistor having a gate electrode and two first source/drain regions and second source/drain regions, the first source/drain regions disposed separately or isolated one after the other along the bit line, adjoining the bit line and each belonging to a further, adjacent vertical MOS transistor, and the second source/drain regions connected to the storage node; a gate oxide adjoining exactly two opposite sides, surfaces or flanks of the gate electrode; two channel regions each adjoining the gate oxide; the gate electrode disposed between the two channel regions; the gate electrodes of adjacent vertical MOS transistors along the word line connected to one another; and the gate electrode and the storage node disposed one under the other.
With the objects of the invention in view, there is also provided a method for the production of a DRAM cell configuration, which comprises producing memory cells each having a read-out transistor and a storage capacitor with a storage node; producing bit and word lines; forming the read-out transistor as a vertical MOS transistor integrated in a substrate of semiconductor material; providing the MOS transistor with two first source/drain regions each belonging to a further, adjacent vertical MOS transistor, disposed separately or isolated one after the other along the bit line and adjoining the bit line, two second source/drain regions each connected to the storage node, and a gate electrode; producing a gate oxide adjoining exactly two opposite sides, surfaces or flanks of the gate electrode; producing two channel regions each adjoining the gate oxide; producing the gate electrode between the two channel regions; electrically connecting the gate electrodes of adjacent MOS transistors along the word line; and placing the gate electrode and the storage node one under the other.
In the DRAM cell configuration according to the invention, single-transistor memory cells are provided in which the read-out transistor is constructed as a vertical MOS transistor. Each MOS transistor encompasses two opposite sides of a gate electrode which run parallel to the word line and adjoin a gate oxide. The MOS transistor has exactly two first source/drain regions, which are disposed spatially separated along a bit line through which they are connected. Each first source/drain region belongs to two neighboring or adjacent transistors along the bit line, which leads to a small cell area.
It is advantageous to realize the storage capacitor in a trench. The outlay for producing such capacitors for the 1 Gbit generation is distinctly less than that for producing planar capacitors or stacked capacitors.
If elements are provided in a self-aligned manner, that is to say without using masks to be aligned, it is possible to achieve a reduction in the cell area since it is not necessary to take alignment tolerances into account. According to one embodiment, the storage nodes are provided in a self-aligned manner under the word lines and are insulated from neighboring storage nodes. In addition, the contacts of the first source/drain regions to the bit lines are opened in a self-aligned manner. This permits the production of cell areas of 4 F2 with just 3 masks.
Second source/drain regions of the MOS transistor are connected to a storage node. They are preferably produced by outdiffusion of dopant from the storage node into a suitable structured layer. As a result, the storage nodes are connected in a self-aligned manner to the second source/drain regions and the cell area is kept small. A junction depth, that is to say the path of minimal separation between source and drain perpendicular to the current flow and perpendicular to the gate electrode, is also kept small, which has a positive influence on short-channel effects, such as punch-through.
It lies within the scope of the invention to construct the gate electrode as part of the word line, which reduces the number of necessary process steps and effects a self-aligned connection between the gate electrode and the word line.
When capacitors realized in trenches are used, it is advantageous to provide a further layer doped by a conductivity type opposite to the conductivity type of the capacitor plate, underneath the layer which serves as a capacitor plate. The substrate is thereby electrically insulated from the capacitor plate, which can be connected separately to a potential.
According to one embodiment, in order not to etch SiO2 too deeply when opening the contacts of the first source/drain regions to the bit lines, which can lead to a short circuit between the word lines and the bit lines, it is advantageous to apply a layer of silicon nitride to the substrate at the beginning of the DRAM production. During the etching of SiO2, the uncovering of the layer of silicon nitride supplies an end-point signal for the etching as a result of a change of physical conditions, such as the gas composition, for instance. In order to avoid superficial damage to the substrate by silicon nitride, it is advantageous to apply a thin SiO2 layer before the silicon nitride layer is produced. Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for the production of a DRAM cell configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.